Dynamic frequency divider with improved leakage tolerance
US7453294B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2005 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Jul 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dynamic frequency divider circuit with improved leakage tolerance supports a wide frequency range. During the evaluation phase, (1) the input signals can be prevented from changing states, (2) the leakage can be reduced, or (3) both can be implemented to generate the correct output signals. In a architecture-level approach, two dynamic flip-flops can be coupled together. In a circuit-level approach, the dynamic flip-flop can include (1) two additional clocked PMOS transistor added to the inputs of the dynamic flip-flop, or (2) two additional pull-up PMOS transistors to counteract the subthreshold leakage in the NMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.