Voltage level shifting circuit, a differential input stage circuit, and a method for providing a level shifted differential signal to a differential input buffer circuit
US7453305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2006 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Sep 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45586
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage level shifting circuit (5) for shifting the common mode voltage of a differential signal to be within the working range of a differential input buffer circuit (3) comprises a first resistive voltage divider circuit (18) coupled between a first input terminal (10) and a voltage reference terminal (15) for receiving a voltage reference to which the common mode voltage of the level shifted differential signal is to be referenced, and a second resistive voltage divider circuit (18) coupled between a second input terminal (11) and the voltage reference terminal (15). The differential signal is applied to the first and second terminals (10,11), and the level shifted differential signal is produced on first and second output taps (17,19) of the first and second resistive voltage divider circuits (16,18) with the common mode of the level shifted differential signal referenced to the voltage reference applied to the voltage reference terminal (15). First and second high frequency low impedance circuits (22,23) couple the first and second input terminals (10,11) to the first and second output taps (17,19) to provide respective direct current blocked high frequency low impedance pat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.