Correlated double sampling ping-pong architecture with reduced DAC capacitors
US7453389B1 · kind B1 · utility
7Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2007 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Aug 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus can be arranged with a correlated double sampler circuit (CDS) for processing an output signal from an imaging device such as a charge-coupled device (CCD) image sensor. The CDS circuit includes an amplifier, a set of capacitors that are dynamically configured for sampling and holding operations, and a reduced number of capacitive digital-to-analog converter (CDAC) circuits, all arranged in a ping-pong architecture. The described ping-pong architecture is useful in digital imaging applications such as digital scanners, digital copiers, digital cameras, and digital camcorders, to name a few.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.