Method and apparatus for predicting system noise
US7454301B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2006 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Oct 6, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/205
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A jitter calculator engine that includes a core effects module, an input/output (I/O) module, and a phase lock loop (PLL) module is provided. The core effects module estimates core jitter caused by noise effects impacting a core clock network. The I/O module estimates I/O input pin switching effects on a clock network input signal. In one embodiment, the I/O module identifies a relative frequency of switching by I/O pins in the circuit design. The PLL module estimates an effect of a PLL on a signal delivered to the PLL from an I/O pin. The PLL module accounts for I/O input pin switching effects and core jitter. The jitter calculator engine may be in communication with a database and the different designs evaluated may be stored in the database so that the database becomes a repository for the different designs and may provide useful information for future designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.