Synchronization and channel deskewing circuitry for multi-channel serial links
US7454537B1 · kind B1 · utility
22Cited by
8References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 22, 2004 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Dec 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The capacity of a single high-speed serial link between programmable logic devices or other integrated circuits may be provided using multiple lower-speed serial links arranged in parallel. Circuitry is provided for synchronizing and deskewing serial data streams from the multiple lower-speed serial links. At a receiving integrated circuit, a first-in-first-out buffer may be associated with each of the lower-speed serial links. Each first-in-first-out buffer may be used to provide both synchronization functions and channel alignment functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.