System and method for cache coherency in a cache with different cache location lengths
US7454576B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2004 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Jul 19, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99952
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. A state tree may be created from data in a sharing vector. When a request arrives from a level one cache, the level two cache may examine the nodes of the state tree to determine whether the node of the state tree corresponding to the incoming request is already active. The results of this determination may be used to inhibit or permit the concurrent processing of the request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.