Method and circuitry for debugging/updating ROM
US7454663B2 · kind B2 · utility
1Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2004 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Apr 6, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read only memory circuit for debugging and updating, the circuit includes read only memory, debug program memory, program counter, and compare and load unit. In the circuit, the compare and load unit detects instruction-read-memory-address from the program counter. If the instruction-read-memory-address is a predetermined main program address, the compare and load unit serves to transmit a debug address in the debug program memory to the program counter to update the original instruction-read-memory-address for debugging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.