Technique for generating input stimulus to cover properties not covered in random simulation
US7454726B2 · kind B2 · utility
2Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2006 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Oct 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/261
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.