Interconnect-aware methodology for integrated circuit design
US7454733B2 · kind B2 · utility
3Cited by
34References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2002 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Mar 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The kit may further include one or more circuit components models and one or more critical interconnect lines models.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.