ASIC clock floor planning method and structure
US7454735B2 · kind B2 · utility
10Cited by
29References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2002 |
| Grant date | Nov 18, 2008 |
| Priority date | — |
| Expiry date | Dec 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks; positioning a temporary reference insertion point (TIP); grouping the sinks together with structured clock buffers (SCBs) in a set of levels; and moving the SCBs to improve symmetry of the tree. The SCBs may be of several sizes and may be positioned horizontally or vertically and moved within limits to permit the program to calculate a complete tree.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.