Nanoscale electric lithography
US7455788B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2006 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Nov 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03G13/286
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A nanoscale lithographic method in which a reusable conductive mask, having a pattern of conductive surfaces and insulating surfaces, is positioned upon a substrate whose surface contains an electrically responsive resist layer over a buried conductive layer. When an electric field is applied between the conductive mask and buried conductive layer, the resist layer is altered in portions adjacent the conductive areas of the mask. Selective processing is performed on the surface of the substrate, after mask removal, to remove portions of the resist layer according to the pattern transferred from the mask. The substrate may be a target substrate, or the substrate may be utilized for a lithographic masking step of another substrate. In one aspect of the invention the electrodes to which the charge is applied are divided, such as into a plurality of rows and columns wherein any desired pattern may be created without the need to fabricate specific masks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.