Vertical thyristor-based memory with trench isolation and its method of fabrication
US7456439B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 2004 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Nov 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/676
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may comprise a plurality of memory cells. A memory cell may comprise a thyristor, at least a portion of which is formed in a pillar of semiconductor material. The pillar may comprise sidewalls defining a cylindrical circumference of a first diameter. In a particular embodiment, the pillars associated with the plurality of memory cells may define rows and columns of an array. In a further embodiment, a pillar may be spaced by a first distance of magnitude up to the first diameter relative to a neighboring pillar within its row. In an additional further embodiment, the pillar may be spaced by a second distance of a magnitude up to twice the first diameter, relative to a neighboring pillar within its column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.