Semiconductor device
US7456446B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2004 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Oct 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source noise are suppressed; wherein a gate electrode formed to have a comb-shaped pattern is formed on a normal cell region, a dummy gate electrode formed to have a comb-shaped pattern is formed on a vacant region, a wiring for applying a predetermined voltage is connected respectively to at least a part of the dummy gate and the semiconductor substrate (source drain regions), and an electrostatic capacity between the part of the dummy gate electrode and the semiconductor substrate constitutes a decoupling capacitor of the power source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.