Phase-locked/frequency-locked loop and phase/frequency comparator therefor
US7456661B2 · kind B2 · utility
5Cited by
8References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 9, 2004 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Jun 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/089
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase/frequency comparator is described which includes two edge-triggered storage elements, each set by an edge of a reference frequency signal of a phase—or frequency-locked loop (PLL) and by an edge of an output frequency signal of the PLL. The storage elements are each reset by an output signal of a resetting logic unit, which is activated when both output signals of the storage elements are activated and then deactivated when the output signals are deactivated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.