Clock systems and methods
US7456672B1 · kind B1 · utility
6Cited by
26References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2006 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Dec 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed herein to provide improved clock, delay, and skew techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a clock generator to provide a bias signal and a clock signal, with control logic providing a delay control signal based on the bias signal and the control signal. A delay circuit provides a delay to the clock signal based on the delay control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.