Semiconductor integrated circuit device for preventing generation of irregular clock signal
US7456675B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 12, 2007 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Feb 12, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A disclosed semiconductor integrated circuit device includes a selection circuit that is supplied with a first clock signal and a second clock signal, a selection signal, and a switching signal, and configured to select one of the first clock signal and the second clock signal according to the selection signal and to change the selected one of the first clock signal and the second clock signal to the other one of the first clock signal and the second clock signal according to the switching signal. The disclosed semiconductor integrated circuit device also includes an output fixing circuit configured to generate a pulse that is maintained at a high level or a low level during a certain period, to perform an OR operation on the output signal from the selection circuit and the generated pulse, and to output a result of the OR operation as the output clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.