Flash memory device having single page buffer structure and related programming operations
US7457158B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2006 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Oct 6, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flash memory device is provided, and the flash memory device comprises memory cells, a sense node connected to a selected bit line, a load circuit connected to the sense node, and first and second sense and register circuits, each connected to the sense node. The first sense and register circuit is configured to store a first data value in accordance with the voltage level of the sense node during an initial read interval of a multi-bit program operation. The load circuit is configured to selectively pre-charge the sense node in accordance with the data value stored in the first sense and register circuit during a verify read interval of the multi-bit program operation. A multi-bit programming method for the flash memory device is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.