Structure for scheduler pipeline design for hierarchical link sharing
US7457241B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2004 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Aug 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.