Lock and release mechanism for out-of-order frame prevention and support of native command queueing in FC-SATA
US7457902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2006 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | May 25, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/387
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A switch connection lock and release mechanism is disclosed to prevent out-of-order frames from being received by FC and/or SATA devices. The mechanism includes a set of previous AL_PA registers, alpa_reg[N:0], one for each port, and a bit vector, prev_conn[M:0], one bit for each Buffer Bank (BB). If a connection is closed prematurely, the valid AL_PA of the destination device and the source port number are stored in the previous AL_PA register associated with the destination port, and the bit in the bit vector associated with the source BB is asserted. Together, the valid AL_PA, the source port and the asserted bit form a connection lock on the destination port that effectively will deny access to the destination port to all BBs with the same destination AL_PA and source port number except the source BB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.