Reducing power consumption in a sequential cache
US7457917B2 · kind B2 · utility
5Cited by
4References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Dec 6, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention includes a cache memory, which may be a sequential cache, having multiple banks. Each of the banks includes a data array, a decoder coupled to the data array to select a set of the data array, and a sense amplifier. Only a bank to be accessed may be powered, and in some embodiments early way information may be used to maintain remaining banks in a power reduced state. In some embodiments, clock gating may be used to maintain various components of the cache memory in a power reduced state. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.