Apparatus and method for using variable end state delay to optimize JTAG transactions
US7457986B2 · kind B2 · utility
2Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2004 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Feb 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a JTAG test and debug environment, the parameters that are accessed by command include a delay parameter. The delay parameter prevents the subsequent command from being executed until both the original command has been executed and the clock cycles indicated by the delay parameter have been completed. Because the time delay is included as a parameter identified by the command, the delay parameter can be programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.