Error correction structures and methods
US7458007B2 · kind B2 · utility
4Cited by
11References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Nov 25, 2008 |
| Priority date | — |
| Expiry date | Oct 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/37
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A syndrome evaluation with partitioning of a received block of symbols into subsets and interleaved partial syndrome evaluations to overcome multiplier latency. Parallel syndrome evaluations with a parallel multiplier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.