Patent · US Active

Electrical interface for memory connector

US7458821B2 · kind B2 · utility

2Cited by

9References

19Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Dan Willis · Pittsburgh, US
David Kraus · Appleton, US

Key dates

Filing date	Dec 7, 2005
Grant date	Dec 2, 2008
Priority date	—
Expiry date	Aug 2, 2026

Classification

Technology area (CPC H)Electricity
CPC primaryH05K2201/10189
WIPO fieldElectrical machinery, apparatus, energy
WIPO sectorElectrical engineering

Abstract

According to some embodiments, a connector to receive a memory module includes a first row of a first plurality of interconnect ends, a second row of a second plurality of interconnect ends adjacent to the first row, and a third row of a third plurality of interconnect ends adjacent to the second row. An interconnect end of the first plurality of interconnect ends, an interconnect end of the second plurality of interconnect ends, and an interconnect end of the third plurality of interconnect ends may be substantially aligned.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.