Patent · US Active

Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors

US7459368B2 · kind B2 · utility

0Cited by
3References
6Claims
0Family size

Assignee

Inventor

Key dates

Filing dateAug 2, 2007
Grant dateDec 2, 2008
Priority date
Expiry dateAug 3, 2027

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/038

Abstract

Method for manufacturing integrated circuits having silicon-germanium heterobipolar transistors, wherein a collector semiconductor region is created, an etch stop layer is created on a connection region, an opening is introduced into this etch stop layer, semiconductor material, which is formed as a single crystal at least in the collector semiconductor region above the opening, is applied over the etch stop layer and over the opening. Before etching of the semiconductor material, a masking layer is applied above the collector semiconductor region to the semiconductor material, which protects the collector semiconductor region from the etching. Afterwards the semiconductor material is etched to the depth of the etch stop layer, the etch stop layer acting as an etch stop such that reaching an interface between the semiconductor material and the etch stop layer is detected during the etching and the etching is stopped depending on the detection.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.