Method for reducing device and circuit sensitivity to electrical stress and radiation induced aging
US7459403B1 · kind B1 · utility
1Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2006 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Sep 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76829
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In microelectronic circuits involving dielectric/semiconductor interfaces having interstitial sites in the dielectric, a method for hardening these interfaces by introducing a small atomic diameter inert gas into the interstitial sites.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.