Nonvolatile semiconductor memory device and manufacturing method of the same
US7459747B2 · kind B2 · utility
4Cited by
3References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2006 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Sep 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention realizes a smaller-sized OTP memory cell and large reduction of its manufacturing process and cost. An embedded layer (BN+) to be a lower electrode of a capacitor is formed in a drain region of a cell transistor of an OTP memory, a capacitor insulation film having a small thickness where dielectric breakdown can occur by a predetermined voltage applied from a data line is formed on this embedded layer, and a conductive layer to be an upper electrode of a capacitor is formed on the capacitor insulation film and on a field oxide film. The embedded layer (BN+) partially overlaps a high concentration drain region (N+).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.