High accuracy sample and hold circuit having a common negative input terminal
US7459943B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2006 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Jan 29, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high accuracy sample and hold circuit including a first switch, a second switch, a first capacitor, a second capacitor and an amplifier is disclosed. The first capacitor receives and saves a sampling voltage from the first switch during a first period, while the second capacitor receives and saves another sampling voltage from the second switch during a second period. The amplifier has first and second positive input terminals, a negative input terminal, an output terminal and a first input stage and an output stage. Wherein, the first input stage includes a first input set and a second input set. During the first period, the amplifier disables the operation of the first input set and enables the operation of the second input set, while during the second period, the amplifier enables the operation of the first input set and disables the operation of the second input set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.