Thyristor-based semiconductor memory and memory array with data refresh
US7460395B1 · kind B1 · utility
37Cited by
18References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2005 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Sep 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in several ways to form different memory arrays. Timing and voltage levels of word, bit and control lines are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.