Method for checking block erasing of a memory and circuit thereof
US7460401B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2006 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Aug 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method checks the state of a set of memory cells of a memory having memory cells arranged in a memory array, row and column decoders for selecting a memory cell, and a sense amplifier for supplying a state of the selected memory cell depending on whether the selected memory cell is conductive or non-conductive. The method includes features wherein all the memory cells of a set grouping together several memory cells are selected, and then simultaneously coupled to the sense amplifier, and the sense amplifier supplies a global state of all the selected memory cells to which it is coupled, if the latter are simultaneously non-conductive. Application is provided to the checking of a command for block-erasing a memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.