Network receive interface for high bandwidth hardware-accelerated packet processing
US7460473B1 · kind B1 · utility
167Cited by
15References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2004 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Jul 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed is a system and methods for accelerating network packet processing for devices configured to process network traffic at relatively high data rates. The system incorporates a hardware-accelerated packet processing module that handles in-sequence network packets and a software-based processing module that handles out-of-sequence and exception case network packets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.