Storage structure and method utilizing multiple protocol processor units
US7460550B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2004 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Jan 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage structure and method having multiple protocol processor units are disclosed. The storage structure comprises a host CPU, a main memory, a storage device, a switch fabric, and a host bus adapter module. The host bus adapter module includes a plurality of protocol processor nodes for processing frames received from a network, and storing those frames into the storage device. A processing module of the host bus adapter module extracts the session information of each frame and compares it with entries recorded in a look-up table. If the connection information hits one entry of the look-up table, the frame can be bypassed into a corresponding protocol processor node according to the definition of the look-up table. Otherwise, a new entry will be inserted into the look-up table for designating a corresponding protocol processor node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.