Electronic circuit for performing fractional time domain interpolation and related devices and methods
US7460587B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 24, 2003 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Dec 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2657
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock offset compensation arrangement may include a fractional interpolator for applying a trigonometric interpolation to a sampled input signal according to a clock offset signal. It uses transform-based processing in the frequency domain. Compared to a polynomial type interpolation it may be easier to implement, and may achieve a closer approximation to an ideal interpolation. It may reduce the effects of non-linear type errors introduced by truncation of higher powers. The arrangement may be applied to receivers or transmitters of multi-carrier modems, as well as other applications which use rate adaptation or synchronization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.