Error diffusion method and hardware architecture
US7460727B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | May 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N1/4052
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system and method for performing threshold stamping are disclosed. First and second threshold values corresponding to first and second pixels may be retrieved from a threshold memory. A plurality of upscaled threshold values may optionally be computed based on the first threshold value and the second threshold value. An (upscaled) threshold value may be updated at each of one or more first register blocks. A binary pixel value may be computed based at least in part on the first updated threshold value. The first updated threshold value may be updated at each of one or more second register blocks. A downscaled threshold value may optionally be computed based on a plurality of second updated threshold values. The downscaled threshold value or second updated threshold value may be damped in a damping circuit, and the damped threshold value may be stored in the threshold memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.