Modular multiplier
US7461115B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2003 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Nov 7, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/725
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Modular multiplication of two elements X(t) and Y(t), over GF(2), where m is a field degree, may utilize field degree to determine, at least in part, the number of iterations. An extra shift operation may be employed when the number of iterations is reduced. Modular multiplication of two elements X(t) and Y(t), over GF(2), may include a shared reduction circuit utilized during multiplication and reduction. In addition, a modular multiplication of binary polynomials X(t) and Y(t), over GF(2), may utilize the Karatsuba algorithm, e.g., by recursively splitting up a multiplication into smaller operands determined according to the Karatsuba algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.