Deferred branch history update scheme
US7461243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2005 |
| Grant date | Dec 2, 2008 |
| Priority date | — |
| Expiry date | Apr 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor comprises a branch prediction array, an index generator coupled to the branch prediction array, and a control unit coupled to the index generator. The branch prediction array is configured to store a plurality of branch predictions for conditional branches. The index generator is configured to generate an index to the branch prediction array responsive to at least a portion of a fetch address corresponding to a fetch request that is at a first pipeline stage of the processor and further responsive to a branch history. The control unit is configured to update the branch history responsive to a first fetch request at the first pipeline stage and to defer the update for a second fetch request to a second pipeline stage subsequent to the first pipeline stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.