Parallel conversion circuit
US7463171B2 · kind B2 · utility
4Cited by
4References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2007 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Mar 26, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a serial-to-parallel conversion circuit that detects phase difference between a timing of receiving serial receive data and reconstituting parallel data for each symbol and a timing of outputting the reconstituted parallel data to an inside of an LSI, and outputs the detected phase difference as delay time information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.