SRAM test method and SRAM test arrangement to detect weak cells
US7463508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2005 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Nov 8, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a test arrangement for testing an SRAM having a first cell and a second cell coupled between a pair of bitlines is disclosed. In a first step, a data value is stored in the first cell being the cell under test (CUT), and its complement is stored in a second cell, being the reference cell. Next, the bitlines are precharged to a predefined voltage. Subsequently, the wordline of the reference cell is enabled for a predefined time period, for instance by providing the wordline with a number of voltage pulses. This causes a drop in voltage of the bitline coupled to the logic ‘0’ node of the reference cell. In a subsequent step, the wordline of the CUT is enabled, which exposes the CUT to the bitline with the reduced voltage. This is equivalent to weakly overwriting the CUT. Finally, the data value in the CUT is evaluated. If the data value has flipped, the CUT is a weak cell. Cells with varying levels of weakness can be detected by varying the reduced voltage on the aforementioned bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.