Multi-level cell serial-parallel sense scheme for non-volatile flash memory
US7463514B1 · kind B1 · utility
11Cited by
7References
15Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 21, 2007 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Jun 21, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5645
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of sensing data in a multi-level cell memory using two or less sense operations and adjusting column load is provided. A sensing circuit implementing a serial-parallel sense scheme is also provided. The column loads are re-configurable based on the sensing circuit and the serial-parallel sense scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.