Node synchronization for multi-processor computer systems
US7464115B2 · kind B2 · utility
12Cited by
5References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2005 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Feb 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.