Methods and apparatus for single stage Galois field operations
US7464128B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2004 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | May 20, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for single function stage Galois field (GF) computations are described. The new single function stage GF multiplication requires only m-bits per internal logic stage, a savings of m−1 bits per logic stage that do not have to be accounted for as compared with a previous two function stage approach. Also, a common design GF multiplication cell is described that may be suitably used to construct an m-by-m GF multiplication array for the calculation of GF[2m]/g[x]. In addition, these techniques are further described in the context of packed data form computation, very long instruction word (VLIW) processing, and processing on multiple processing elements in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.