Logic circuit and method for performing AES MixColumn transform
US7464130B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 4, 2003 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Aug 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A logic circuit having structure for performing the AES Rijndael MixColumns transform exploits the relationship between each successive row of the transform matrix and its preceding row. Multiplication of an (m.times.n) matrix by a (1.times.n) or by a (m.times.1) matrix is performed, where m is a number of rows and n is a number of columns, and where each successive row, m, of n elements is a predetermined row permutation of a preceding row, includes: n multiplication circuits; n logic circuits; n registers for receiving logical output from the logic circuits; feedback logic for routing contents of each register to a selected one of inputs of the logic circuits in accordance with a feedback plan that corresponds to the relationship between successive matrix rows; and a control unit for successively providing as input to each of the n multiplication circuits each element in the (1.times.n) or (m.times.1) matrix.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.