Systems and methods for driving data over a bus where the systems employ a bus clock that is derived from a system clock and a data clock designed to lead the bus clock
US7464284B2 · kind B2 · utility
4Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2005 |
| Grant date | Dec 9, 2008 |
| Priority date | — |
| Expiry date | Mar 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for driving data over a data bus are disclosed. One embodiment of a system may comprise a bus clock signal that is a copy of a system clock signal that controls the timing associated with transferring data over the bus, a data clock signal that is designed to lead the system clock by a portion of a clock cycle to drive data over the bus ahead of the bus clock signal, an output latch device that drives data over the data bus in response to an edge of the data clock signal and a skew corrector that mitigates racing of data over the data bus in the event that the data clock lags the bus clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.