Look-up table structure with embedded carry logic
US7466163B2 · kind B2 · utility
3Cited by
12References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 19, 2007 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Nov 19, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01H9/40
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A configurable look up table (LUT) structure of an integrated circuit comprising: a first, a second and a third intermediate LUT stage, each of the LUT stages comprising one or more inputs and an output, wherein: the output of first intermediate LUT stage is coupled to an input of the second and third intermediate LUT stages; and the second intermediate LUT stage generates an arithmetic function of two bits and a carry-in signal received as inputs to the LUT structure; and the third intermediate LUT stage generates a carry-out signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.