DC offset mitigation in a single-supply amplifier
US7466194B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2007 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Jun 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/2173
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier is described which includes a first loop including a first amplifier stage having an offset voltage associated therewith. An output stage includes two switching devices in a bridge configuration configured to be coupled between a supply voltage and ground. An output of the bridge configuration is configured to be coupled to a load. The first loop is characterized by a first gain. A decoupling capacitor is configured to be coupled to the load. A second loop which includes the first amplifier stage is configured to charge the decoupling capacitor to a first voltage generated with reference to the offset voltage before operation of the switching devices is enabled. The second loop is characterized by a second gain. The first and second gains are substantially the same such that when operation of the switching devices is enabled a second voltage at the output of the half-bridge configuration is substantially the same as the first voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.