Chip seal ring having a serpentine geometry
US7466284B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2006 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Jan 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A chip seal ring that maintains the chip seal ring as a continuous barrier to contamination, while at the same time creating a desirable electrical feature in the seal ring that enables the use of an on-chip loop antenna. In one embodiment, at least a portion of the chip seal ring has a serpentine configuration, such as a square wave, triangle wave, or curved geometry, that increases the reactance and resistance of the seal ring so as to mitigate the adverse induced currents created by the magnetic coupling effects between the on-chip antenna and the seal rings, thereby improving the efficiency of an on-chip loop antenna in the presence of the seal ring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.