Impedance-matched write circuit with shunted matching resistor
US7466508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2004 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Dec 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B2005/0013
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An impedance matched write circuit is provided that shunts one or more matching resistors. The impedance matched write circuit includes an interconnect for connecting to a write head and at least one resistor between a control voltage and the interconnect for impedance matching to the interconnect. A transistor can be connected across the resistor to shunt current that would otherwise pass through the resistor during an overshoot mode. The transistor may be a PMOS transistor or a combination of PMOS and NMOS transistors. A gate voltage of the transistor is controlled by a source such that the transistor is turned on in an overshoot mode and turned off during a steady state mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.