Sense amplifier for flash memory device
US7466613B2 · kind B2 · utility
1Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2005 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Aug 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier circuit comprises first and second cross-coupled inverters to produce a latch with first and second power supply nodes. The first latch power supply node couples a first power supply potential to the latch when the sense amplifier is operating in a read-out mode. The second latch power supply node couples a second power supply potential to the latch when the sense amplifier operates in the read-out mode. The first and second latch power supply nodes are further configured to couple an equalization potential to the first and second power supply nodes when the latch is operating in an equalization mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.