System and method for low power wordline logic for a memory
US7466620B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Apr 11, 2006 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Oct 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of reducing power consumption of a memory is provided. A request is received to access a memory device, including a decoder, a plurality of wordline drivers and a plurality of wordlines. Each wordline is associated with a wordline driver of the plurality of wordline drivers. The request is decoded by a decoder to determine an address associated with the request. A wordline driver of the plurality of wordline drivers is selectively powered to access the address of the memory device, where the wordline driver is associated with a particular wordline of the plurality of wordlines that is related to the address bits, without powering other wordlines of the plurality of wordlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.