Method and apparatus for aligning multiple outputs of an FPGA
US7467056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2007 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Mar 9, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Each data lane connected to a FPGA and forming part of a SFI channel may be trained independently to enable the outputs from the FPGA to be aligned. In operation, a known fixed pattern is repeated on each of the data lanes with the exception of the data lane being trained. The short fixed pattern is smaller than an SERDES capture range so that the SERDES may temporarily lock onto the short fixed pattern for all data lanes other than the lane being trained. Training data is then transmitted on the lane being trained and the preskew delay for that lane is adjusted until the receiving component indicates that the lanes are aligned. This process may iterate to find acceptable preskew delay values for all lanes. By training the lanes one at a time and using a short repeating pattern on the untrained lanes, the SERDES may register that the untrained lanes are operating correctly so that the feedback from the SERDES is related only to the lane being trained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.