Processing unit having decimal floating-point divider using Newton-Raphson iteration
US7467174B2 · kind B2 · utility
17Cited by
10References
20Claims
0Family size
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Key dates
| Filing date | Nov 5, 2004 |
| Grant date | Dec 16, 2008 |
| Priority date | — |
| Expiry date | Dec 7, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5355
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A decimal floating-point divider is described that implements efficient hardware-based techniques for performing decimal floating-point division. The divider uses an accurate piecewise linear approximation to obtain an initial estimate of a divisor's reciprocal. The divider improves the initial estimate of the divisor's reciprocal using a modified form of Newton-Raphson iteration. The divider multiplies the estimated divisor's reciprocal by the dividend to produce a preliminary quotient. The preliminary quotient is rounded to produce the final decimal floating-point quotient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.